Ansys medini analyze for Semiconductors
Functional Safety Analysis for Semiconductors
Ansys medini analyze supports key safety analysis methods at various levels of a chip, ranging from IP Design of integrated components, up to SoCs and electronic boards.
SEMICONDUCTOR-LEVEL SAFETY ANALYSIS
Semiconductor Analysis Integrated With Overall Systems Analysis
Ansys medini analyze supports best-practice workflows that graphically link specific areas of the semiconductor design to key functions within the electronics architecture. This allows engineers to analyze and address potential failure modes as they verify the functional safety of semiconductor components. Engineers can efficiently and consistently execute the safety-related activities such as the FMEDA, required by safety standards like ISO 26262: 2018 part 11.
-
Failure Rate Prediction
-
Map Chip Design to Functions
-
Failure Mode Effect and Diagnostic Analysis
-
Digital and Analog Chip Analysis
Quick Specs
Streamline and automate functional safety analysis across the entire electronics architecture — including down to the chip level. Any inconsistencies in the functional safety analysis are eliminated, and confirmation reviews and assessments are accelerated.
-
Failure Rate Distribution by Die Area -
Requirement Traceability -
IP Design Import
-
Determine and Analyze Potential Failure Modes -
FMEDA -
Safety Mechanism Design
-
Map Blocks of the Semiconductor Design to System Functions -
Transient Failure Analysis -
Diagnostic Coverage Analysis
Chipping Away at Functional Safety Flaws in Automotive Electronics
Reduce development costs and time to market, while maximizing innovation and product confidence.
As regulatory guidelines and requirements change, it’s essential for automotive engineering teams to have best practices and leading-edge technology tools in place to manage the growing challenge of compliance. In response to changes in ISO 26262 that shine a spotlight on the functional safety of semiconductors, Ansys medini analyze is ready with new capabilities to facilitate and automate this analysis.
Companies that cling to outdated manual processes and consumer-grade tools that weren’t designed for functional safety analysis will be challenged to remain competitive as regulations become more and more stringent. In contrast, engineering teams that embrace best-in-class software solutions from Ansys — and the power of automated analysis and documentation — will be much faster to market with more innovative, more profitable electronic systems designs that meet both consumer demands and new regulatory guidelines.
CAPABILITIES
Ansys medini analyze for Semiconductors Facilitates Analysis at Various Levels of a Chip
With Ansys medini analyze for semiconductor safety , seamlessly exchange IP design between hardware designers and safety analysts. Engineers can perform derivation of base failure rates for a hardware design, automatic determination of failure distributions based on design data (e.g., die area, gate counts), as well as FMEA, FMEDA and FTA analysis based on the hardware design. Teams can reuse and adapt FMEDA data from previous designs and export configurable FMEDA result data for the handover of safety data to integrators.
Key Features
By reducing development costs and time to market — while maximizing innovation and product confidence — Ansys medini analyze can help companies achieve a significant competitive advantage
- Model-Based Safety Analysis
- Integrated Reliability Prediction
- Teamwork and Supply-Chain Support
- Traceability and Validation
Implement qualitative methods (e.g., FMEA, quantitative analysis, failure rate prediction, FMEDA and diagnostic coverage analysis, or FTA), as well as dependent failure analysis. These methods are integrated and carried out at various levels over a consistent set of design models.
ISO 26262 Semiconductor Workflow Ansys medini analyze facilitates ISO 26262 compliance and remains a trusted solution for streamlining and automating functional safety analysis across the entire electronics architecture, down to the chip level.
Predict failure rates of your chips using built-in handbooks such as IEC 61709, IEC 62380, SN29500, and many more. Distribute failure rates along die area or element/gate/cell counts of an imported IP design, both for permanent and transient failures. Define stress parameters such as temperature and analyze the impact for FMEDA and PMHF to meet safety and reliability targets.
Collaborate as a safety engineering team by sharing, comparing and merging safety projects. Integrate with task management systems for workflow support. Export your safety analysis (e.g. FMEDA) in a configurable way to field teams and customers for adaptation to the target system context
Capture and trace your safety requirements together with your chip design. Import, export and round-trip from/to requirements management for systems (e.g., IBM® Rational® DOORS®, PTC Integrity™, Jama Software) and design tools such as Cadence Incisive Simulator or Synopsys IC Compiler. Validate the standard compliance of your safety mechanisms with fault injection by third-party verification tools.
RESOURCES & EVENTS
Brochures
White Papers
Webinars On Demand
Blogs
Ansys software is accessible
It's vital to Ansys that all users, including those with disabilities, can access our products. As such, we endeavor to follow accessibility requirements based on the US Access Board (Section 508), Web Content Accessibility Guidelines (WCAG), and the current format of the Voluntary Product Accessibility Template (VPAT).
See What Ansys Can Do For You
See What Ansys Can Do For You
Contact Us
Contact us today
